As is well known in this specific technical field, a Phase Locked Loop (PLL), as generally shown at 1 in FIG. 1, comprises essentially a phase comparator 2, a filter 3, a frequency divider 4, and a voltage controlled oscillator VCO 5.
With the phase locked loop (PLL) 1 locked to a periodic input signal at a frequency Fref, the frequency Fvco of the voltage controlled oscillator VCO 5 is equal to that of the input signal multiplied by a division ratio N of the frequency divider 4.
The phase comparator 2 generates a signal which is proportional to the phase difference between the input signal and the output signal of the frequency divider. This signal modifies, through the filter 3, the control voltage of the voltage controlled oscillator VCO 5, and consequently its frequency Fvco as well, thereby bringing the output frequency Fdiv of the frequency divider 4 to the same value as the input frequency Fref.
The characteristic parameters according to which a phase locked loop (PLL) 1 is evaluated are the following:                accuracy of the generated frequency;        phase noise;        glitch rejection;        locking time; and        loop phase margin.        
The frequency accuracy of the voltage controlled oscillator VCO 5 is dependent on the frequency accuracy of the input signal and the accuracy of the phase comparator 2.
A PLL has two main behaviors: in tracking mode the PLL has already locked on to the signal; what the PLL does to keep itself aligned with the incoming signal in light of frequency and phase disturbance in this modality.
On the contrary, in acquisition mode the PLL is either out of clock or in start up phase. This phase is difficult to analyze and understand but the good performance of a system is also based on the time spent to get all parameters to lock the PLL, the rapidity of the convergence.
Up to now the prior systems for clock synthesis or data timing recovery don't provide any solution for completely skipping the transient time that is needed for the locking of the system. More particularly, all prior art solutions present a drawback due to the presence of analogous components requiring a predetermined time to get all parameters for locking the PLL.